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OpenBIC

BICs (Bridge IC) are standalone devices deployed within a Data Center that enable monitoring a multi-host system using a single BMC device.

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68 stars62 forks85 contributorsActive · 6h agoSince 2021oby35-hd-2022.37.01Apache-2.0

Meet the team

See all 85 on GitHub →
SaraSYLin
SaraSYLin269 contributions
LoraLin1
LoraLin1242 contributions
MouchenHung-QUANTA
MouchenHung-QUANTA182 contributions
Yi-Shum
Yi-Shum163 contributions
GoldenBug
GoldenBug162 contributions
Victor-Jhong
Victor-Jhong159 contributions
MarshallZhan-wiwynn
MarshallZhan-wiwynn136 contributions
LisaChang-Quanta
LisaChang-Quanta127 contributions

Languages

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C99%
Python0.6%
CMake0.4%
Shell0%

Commit activity

Last 12 weeks · 38 commits

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Community health

4 of 6 standards met

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Recent PRs & issues

Active · 1 in progress · Last activity 6h ago
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wrouwet
[Experimental] mcx-n9xx-evk: OpenBIC on mainline Zephyr for NXP MCX-N9XX-EVKOpenPR

Summary This is an experimental proof-of-concept, not a request to merge a finished board. It demonstrates that OpenBIC's core stack - IPMI dispatch, IPMB transport, MCTP, PLDM, the sensor framework, FRU - is portable to mainline Zephyr ( v4.4.0), running on an SoC family (NXP MCX-N9xx) with no Aspeed/Nuvoton relationship at all, instead of the vendor-forked Zephyr trees every existing OpenBIC board depends on. I'm opening this mainly to get a read from maintainers on whether this direction is of any interest to the project, not because I think it's ready to merge as-is. Full writeup, including exactly what's real vs. stubbed and why, is in on this branch. What's genuinely verified on real hardware Real // code (not stand-ins) for watchdog, timer, I2C, sensor framework, FRU, MCTP, PLDM. A real IPMI/IPMB transport: and needed almost no changes - the only Aspeed-specific piece was the bottom-edge I2C-slave integration, replaced with mainline's own API. A shell self-test round-trips a real Get Device ID request through the actual dispatch pipeline (queues, threads, netfn routing, handler) and every response byte matches expected values exactly. Boots clean, IPMB TX/RX threads start on real target-mode I2C hardware, dual-core mailbox IPC between the SoC's two Cortex-M33 cores, NVS persistent storage, GPIO monitoring, watchdog-triggered reset - all demonstrated on physical hardware, not just compiled. What's explicitly NOT done / still open No real sensors wired up - the EVK has none, so the sensor/SDR tables are genuinely empty. Wire-level IPMB transaction: untested, not confirmed working. A jumper-wire test between this board's own two I2C instances showed an unresolved signal-integrity anomaly (documented in the README) - properly resolving it needs an oscilloscope or a second real device, neither available here. IPMI transport for a real host (KCS/SSIF) isn't attempted - no mainline equivalent exists, and there's no host on this EVK to talk to. Meta's proprietary OEM-1S command set (fan/GPIO/JTAG/PECI/APML) is stubbed, not ported, for the same "no applicable hardware" reason. I3C, and a real GPIO driver for this SoC, are out of scope - see the README for the specific mainline driver issues hit. This currently depends on an unmerged upstream fix** (zephyrproject-rtos/hal_nxp#799) for a real divide-by-zero in NXP's vendored HAL, pulled in via a manifest override pointing at my fork in the meantime. Test plan [x] builds clean from a fresh (no manual patching). [x] Flashed and verified boot banner, shell, and all subsystem init log lines on a real MCX-N9XX-EVK over its MCU-Link VCOM console. [x] shell command verified correct, byte-exact IPMI Get Device ID response through the real dispatch pipeline. [ ] Wire-level IPMB transaction between two real devices - not possible with the hardware available for this port; see README. Happy to answer questions or adjust scope/direction based on maintainer feedback.

wrouwet · 4h ago

Recent fixes

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khoung76642
sb: rb: add svs functions and fix some issueMergedPR

Summary: add 312.5Mhz APLL lock status can get from shell cmd: "clock_status get all" add read svs_core_voltage from shell cmd: "rb_asic svs_core_voltage_get" fix ioe set bootstrap table issue fix shell voltage set rail name error add shell cmd to read medha0/1 vout offset value add vout set/get will follow svs_flag to set/get same as i2c target 0x88 0x89 modify some issue and add read vout offset when power on Test Plan: Build code: Pass

khoung76642 · 8h ago
Joseph-Shih-ww
scripts: signing: Add GC2 platform supportMergedPR

[Task Description] Add GrandCanyon V2.0 (GC2) platform support to BIC image signing. Add GC2 server board mapping for signed BIC images. [Motivation] GC2 requires BIC images to include the correct project and board identity information during image signing. [Solution] Add to the supported project list. Add board mapping for GC2. Add the GrandCanyon V2.0 project name mapping.

Joseph-Shih-ww · 3d ago
Joseph-Shih-ww
gc2: es: Version Commit for 2026.34.01MergedPR

Summary: Description Version commit for Emerald Springs BIC obgc2-es-v2026.34.01 Motivation Version commit for Emerald Springs BIC obgc2-es-v2026.34.01

Joseph-Shih-ww · 3d ago
Structured data for AI agents

Repository: facebook/OpenBIC. Description: BICs (Bridge IC) are standalone devices deployed within a Data Center that enable monitoring a multi-host system using a single BMC device. Stars: 68, Forks: 62. Primary language: C. Languages: C (99%), Python (0.6%), CMake (0.4%), Shell (0%). License: Apache-2.0. Latest release: oby35-hd-2022.37.01 (3y ago). Open PRs: 1, open issues: 5. Last activity: 6h ago. Community health: 75%. Top contributors: SaraSYLin, LoraLin1, MouchenHung-QUANTA, Yi-Shum, GoldenBug, Victor-Jhong, MarshallZhan-wiwynn, LisaChang-Quanta, HungYi-Li, Quanta-YangChen and others.

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